Mission Statement

     Our mission is to deliver a comprehensive portfolio of innovative and non-intrusive integrated software solutions that provide the ability to increase the overall output of semiconductor device manufacturing at higher quality levels and with lower costs.

     Acuity is defined as the capacity of the eye to see fine detail, measured by determining the finest detail that can just be detected.

     Test Acuity Solutions (TAS) develops and deploys leading-edge, proprietary software focused on exposing device performance variability across the semiconductor back-end manufacturing processes, to automate manufacturing quality and facilitate equipment utilization and process improvements throughout the manufacturing process

     Our solutions have repeatedly proven that no trade-off is automatically necessary between device quality and the cost of test.

Technology attributes:

• Die grading and die disposition technology based on performance variability analysis of Wafer Fab and Test Data
• Wafer level disposition technology based on regional spatial and automatic pattern detection analysis
• End-to-end connectivity using open-standards enabling Adaptive Test and Adaptive feed-forward, Single Device Traceability (SDT) and Intelligent Recall through technology partnership with Kinesys Software.
• Corporate-wide test quality and efficiency standards throughout the semiconductor product lifecycle

     Test Acuity Solutions (TAS) patented and patent pending proprietary technologies exposes device marginality and enables next generation feed-forward and adaptive test strategies that are being recognized industry-wide as necessary technologies to achieve next generation cost and quality models.

     Our solutions provide the technology to enable downstream process flow decisions through the application of adaptive feed-forward methodologies as represented in the International Technology Roadmap for Semiconductors (ITRS).

Source: International Technology Roadmap for Semiconductor (ITRS), Adaptive test Subgroup, Test & Testability Section

These methods are becoming even more critical as the industry drives toward the integration of known good die in 3D multi-chip packaging technologies.